• Parallel Input Serial Output Shift Register Verilog Codes

Design of Parallel IN - Serial OUT Shift Register using Behavior Modeling Style -

The output of the register is N bits (in our example we will use a 4 bit register). It has an N-bit Parallel input, which allows us to load the register with a new value. The load_shift signal allows us to determine the operating mode: when it is at 0, a new value is loaded when a rising edge of the clock arrives.

Output Waveform : Parallel IN - Serial OUT Shift Register

VHDL Code-
-------------------------------------------------------------------------------
--
-- Title : parallel_in_serial_out
-- Design : vhdl_upload2
-- Author : Naresh Singh Dobal
-- Company : nsdobal@gmail.com
-- VHDL Programs & Exercise with Naresh Singh Dobal.
--
-------------------------------------------------------------------------------
--
-- File : Parallel IN - Serial OUT Shift Register.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity parallel_in_serial_out is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC
);
end parallel_in_serial_out;
architecture piso_arc of parallel_in_serial_out is
begin
piso : process (clk,reset,load,din) is
variable temp : std_logic_vector (din'range);
begin
if (reset='1') then
temp := (others=>'0');
elsif (load='1') then
temp := din ;
elsif (rising_edge (clk)) then
dout <= temp(3);
temp := temp(2 downto 0) & '0';
end if;
end process piso;

Parallel Input Serial Output Shift Register Verilog Codes

end piso_arc;